Researchers develop new p-type semiconductor materials for next-generation displays

A group of Korean researchers recently succeeded in developing new p-type semiconductor materials and thin-film transistors that will be at the forefront of innovation in the semiconductor industry. These new findings are expected to be widely used to improve the overall performance of next-generation displays and ultra-low-power semiconductor devices.

The Electronics and Telecommunications Research Institute (ETRI) has successfully developed a p-type Se-Te (selenium-tellurium) alloy transistor that can be easily deposited at room temperature via a simple process using a chalcogenide-based p-type semiconductor material. In addition, they have also developed a new technology that can systematically adjust and control the threshold voltage of n-type transistors through charge injection control of Te thin films in the heterojunction structure of n-type oxide semiconductor and p-type Te.

The work is published in the journal ACS Applied Materials and Interfaces.

Semiconductors are generally classified into intrinsic semiconductors and extrinsic semiconductors based on their “doping status.” In other words, intrinsic semiconductors are “pure” semiconductors with no added impurities. In the case of silicones, a commonly used material in the semiconductor industry, no electrons can move in pure silicone, meaning that no current flows even when a voltage is applied.

Therefore, specific impurities are added to the intrinsic semiconductor to exploit the characteristics of the semiconductor and the electrical conductivity of the materials. Extrinsic semiconductors are divided into n-type semiconductors and p-type semiconductors according to the type of impurities added during the production/manufacturing process.

One of the most widely used materials in today’s display industry is the indium gallium zinc oxide (IGZO) semiconductor. In the case of p-type semiconductors, p-type LTPS (low-temperature polycrystalline silicon) is used due to the lack of ease of processing and electrical properties compared to n-type oxide semiconductors, but it has always had many limitations as it is much more expensive to manufacture and the substrate size is limited.

However, with the increasing demand for higher refresh rates (240Hz+) in high-resolution displays, especially in SHV-class (8K*4K) resolution displays, the interest in developing pa-type semiconductors is reaching its peak in recent years. Since n-type semiconductor-based transistors, which have been used in existing displays, have limitations in efficiently implementing displays with high refresh rates, the demand for p-type semiconductors is increasing at a rapid pace.

To address these needs, ETRI researchers have successfully developed a p-type semiconductor by adding Te to Se, increasing the crystallization temperature of the channel layer, depositing an amorphous thin film at room temperature, and crystallizing it through a subsequent heat treatment process. As a result, they have achieved improved mobility and a higher level of on-line/off-line current ratio characteristics compared to existing transistors.

The researchers also confirmed that when a Te-based p-type semiconductor was introduced as a heterojunction structure on an n-type oxide semiconductor thin film, the threshold voltage of the n-type transistor could be adjusted by controlling the electron flow in the n-type transistor according to the thickness of Te. In particular, they improved the stability of the n-type transistor without the need for a passivation layer by adjusting the thickness of Te in the heterojunction structure.

Using these achievements, the growth of the next-generation display industry is expected to reach new heights, enabling the development of new displays with higher resolution and lower power consumption at the same time.

In fact, this new discovery can not only make significant contributions to the field of display, but it can also change the landscape of the semiconductor industry. Currently, many leading global semiconductor manufacturers are focusing on developing new scale-down processes that can increase the integration of their products, but according to the analysis of many industry insiders, the level of integration in semiconductors has reached its limit.

As a result, in recent years, a new integration method has been introduced to stack multiple semiconductor chips at a time. Among them, the TSV (Through Silicon Vias) method is the most famous, where multiple wafers are stacked and a hole is drilled in the wafers to ensure electrical connection. This TSV method has the advantage of efficient space utilization and low power consumption. However, many limitations still need to be considered, including high process costs, low yield, etc.

In fact, to overcome these limitations of TSV, the industry has come up with a new approach, also known as monolithic three-dimensional (M3D) integration, where materials are stacked on a single wafer instead of stacking multiple layers at a time. Unfortunately, the M3D method has not yet reached its commercialization stage due to various issues such as limited use of high-temperature processes, etc.

However, many experts believe that the heterojunction thin-film transistor and p-type semiconductor device developed by ETRI can operate stably even in processes below 300℃, pushing the industry one step closer to the successful commercialization of M3D.

Cho Sung-Haeng, principal investigator of ETRI’s Flexible Electronics Research Section, said, “This is a monumental achievement that can be widely used in next-generation displays such as OLED TVs and XR devices, as well as by future researchers in other fields such as CMOS (complementary metal-oxide semiconductor) circuits and DRAM memories.”

ETRI researchers said they plan to optimize Te-based p-type semiconductors for large substrates of 6 inches or more and secure their commercialization potential by applying them to various circuits, ultimately finding new ways to implement them in new areas.