New framework designs scalable 3D transistors based on 2D semiconductors

Conventional silicon-based electronics are approaching their limits in terms of performance and scalability. In recent years, engineers have therefore attempted to introduce alternative designs that could help reduce the size of electronic components while improving their speed and energy efficiency.

Researchers at the University of California, Santa Barbara have designed a new framework that could contribute to this quest, enabling the fabrication of scalable three-dimensional (3D) field-effect transistors (FETs) based on two-dimensional layered semiconductors (2D). The proposed approach, described in Natural electronicsrepresents key factors that can influence the performance of these transistors, including Schottky contact effects and inclusive capacitance.

“Our research group was one of the first contributors to highlight the importance of a multi-gate architecture to achieve realistic sub-10nm FETs, even with atomically thin channels based on 2D semiconductors,” said Kaustav Banerjee, lead author of the paper. in an interview with Tech Xplore.

“This prospect has been further explored in our recent work on future transistors, where we collaborated with leading experts from the semiconductor industry to highlight the potential of three-dimensional transistors.”

The main goal of Banerjee and colleagues’ recent work was to demonstrate the potential of atomically thin 2D layered materials for the fabrication of next-generation 3D FETs with various architectures. Additionally, the researchers hoped to better understand what materials, architectures, and designs would be optimal for these transistors.

During their study, they discovered that 2D materials can also be uniquely designed to create an entirely new transistor architecture, which they named nanoplate FET (NPFET). This architecture could feature improved performance and greater integration density.

“The proposed framework for 3D-scale transistor design involves the use of a quantum transport formalism to simulate carrier transport, using a computer-aided design (TCAD) tool available in the trade called QTX,” Banerjee explained. “This tool leverages the nonequilibrium Green’s function framework (NEGF), one of the most powerful quantum transport approaches.”

For different variants of NEGF function, researchers used an efficient mass-based approach. This method has been shown to be computationally efficient and accurate, while also accounting for non-parabolism effects of energy bands, satellite valleys, and the finite energy width of these valleys.

“These input parameters were calculated with density functional theory (DFT) simulations, an ab-initio method, and then imported into QTX,” Banerjee said. “We also considered the effect of non-ideal contact resistance and carrier mobility to perform more in-depth simulations.”

The simulation results performed by the researchers suggest that 3D FETs based on 2D semiconductors can achieve higher performance than silicon-based FETs. The channel length of these 3D FETs based on 2D materials was reduced to around 7nm or less and the material that generated the largest gains was WS.₂.

“Increased drive current, coupled with reduced device capacitance due to the thinness of the 2D semiconductor compared to silicon, improves the overall energy delay product (EDP) of circuits designed with transistors at 2D semiconductor base,” Banerjee said. “Additionally, we have provided a comprehensive blueprint for designing 3D FETs based on 2D semiconductors to support future CMOS scaling.”

To scale transistors, the new NPFET architecture introduced by this research team exploits the thinness and vertical stacking of 2D semiconductors. Compared to comparable 3D-FET architectures introduced in previous studies, this architecture could offer significant advantages in terms of integration density and performance.

“Our future research efforts will focus on close collaboration with industrial partners to accelerate the integration of these materials and designs into traditional CMOS processes,” Banerjee added. “Additionally, we aim to improve our simulations by incorporating a wider range of non-ideal effects, such as defect diffusion and self-heating. This will provide deeper insights and support to experimental researchers in this area .”

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