Integrate dimensions to make the most of Moore’s law and advance electronics

Moore’s Law, the fundamental principle of scaling electronic devices, predicts that the number of transistors on a chip will double every two years, ensuring more computing power, but there is a limit.

Today’s most advanced chips house nearly 50 billion transistors in a space no bigger than your thumbnail. According to the Penn State researchers, the task of cramming even more transistors into this confined area has become increasingly difficult.

In a study published in NatureSaptarshi Das, associate professor of engineering sciences and mechanics and co-corresponding author of the study, and his team suggest a remedy: seamlessly implement 3D integration with 2D materials.

In the semiconductor world, 3D integration means vertically stacking multiple layers of semiconductor devices. This approach not only facilitates the packing of a larger number of silicon-based transistors onto a computer chip, commonly referred to as “More Moore”, but also allows the use of transistors made from 2D materials to incorporate various functionalities into different layers of the stack, a concept known as “More Than Moore”.

With the work described in the study, Saptarshi and the team demonstrate feasible pathways beyond scaling current technology to achieve both More Moore and More than Moore through monolithic 3D integration . Monolithic 3D integration is a manufacturing process in which researchers directly fabricate the devices on top of the one below, compared to the traditional process of stacking independently fabricated layers.

“Monolithic 3D integration offers the highest density of vertical connections because it doesn’t rely on bonding two pre-structured chips together, which would require microbumps where two chips are bonded together, so you have more space to making connections,” said Najam Sakib, a graduate research assistant in engineering sciences and mechanics and co-author of the study.

Monolithic 3D integration, however, faces significant challenges, according to Darsith Jayachandran, a graduate research assistant in engineering sciences and mechanics and co-corresponding author of the study, because conventional silicon components would melt under the temperatures treatment.

“One of the challenges is the process temperature ceiling of 450 degrees Celsius (C) for back-end integration of silicon-based chips. Our monolithic 3D integration approach brings this temperature down significantly to less of 200 C,” said Jayachandran, explaining that the ceiling process temperature is the maximum temperature allowed before damaging prefabricated structures. “Incompatible process temperature budgets make monolithic 3D integration difficult with silicon chips, but 2D materials can withstand the temperatures needed for the process.”

The researchers used existing techniques for their approach, but they are the first to achieve monolithic 3D integration at this scale using 2D transistors made with 2D semiconductors called transition metal dichalcogenides.

The ability to stack devices vertically in 3D integration also enabled more energy-efficient computing because it solved a surprising problem for things as tiny as the transistors in a computer chip: distance.

“By stacking devices vertically on top of each other, you reduce the distance between devices, and therefore, you reduce lag as well as power consumption,” said Rahul Pendurthi, graduate research assistant in health sciences. engineering and mechanics and co. -corresponding author of the study.

By reducing the distance between the devices, the researchers obtained “More Moore”. By incorporating transistors made with 2D materials, the researchers also met the “More than Moore” criterion. 2D materials are known for their unique electronic and optical properties, including their sensitivity to light, making them ideal as sensors. This is useful, researchers say, because the number of connected devices and edge devices (things like smartphones or wireless home weather stations that collect data at the “edge” of a network ) continues to increase.

“‘More Than Moore’ refers to a concept in the technology world that we are not only making computer chips smaller and faster, but also with more features,” said Muhtasim Ul Karim Sadaf, a graduate research assistant in engineering sciences and mechanics and co-author of the study. “It’s about adding useful new features to our electronic devices, like better sensors, improved battery management or other special functions, to make our gadgets smarter and more versatile.”

Using 2D devices for 3D integration has several other advantages, the researchers said. One is higher carrier mobility, which refers to how an electric charge is transported in semiconductor materials. Another is being ultra-thin, which allows researchers to install more transistors on each level of the 3D integration and obtain more computing power.

While most academic research focuses on small-scale prototypes, this study demonstrated 3D integration at large scale, characterizing tens of thousands of devices. According to Das, this achievement bridges the gap between academia and industry. Advances in scaling have been enabled by the availability of high-quality, wafer-scale transition metal dichalcogenides developed by researchers at the Two-Dimensional Crystal Consortium (2DCC-MIP ) from Penn State, a materials innovation hub of the U.S. National Science Foundation (NSF) and national organization. user installation.

“This advancement once again demonstrates the critical role of materials research as the foundation of the semiconductor industry and U.S. competitiveness,” said Charles Ying, director of the U.S. Platforms Program. NSF materials innovation. “Years of efforts by Penn State’s Two-Dimensional Crystal Consortium to improve the quality and size of 2D materials have enabled 3D integration of semiconductors at a size that can be transformative for electronics.”

According to Das, this technological advancement is only the first step.

“Our ability to demonstrate, at wafer scale, a large number of devices shows that we have been able to translate this research to a scale that can be appreciated by the semiconductor industry,” Das said. “We have installed 30,000 transistors in each level, which could be a record number. This puts Penn State in a very unique position to lead some of the work and partner with the U.S. semiconductor industry to advance this research.”