First carbon nanotube-based tensor processor chip could lead to energy-efficient AI processing

Artificial intelligence (AI) and machine learning tools have proven to be very effective in tackling various tasks that involve analyzing data and making accurate predictions. Despite their advantages, these tools require significant computing resources and, when running on existing processing units, can consume a lot of energy.

Researchers from Peking University and other institutes in China have recently developed a very promising tensor processing unit (TPU) based on carbon nanotubes that could be used to run AI algorithms in a more energy-efficient manner. This carbon nanotube-based tensor processing chip, presented in a paper published in Natural electronicscould be a major step forward in the development of next-generation chips.

“We have successfully developed the world’s first tensor processor chip (TPU) based on carbon nanotubes,” Zhiyong Zhang, co-author of the study, told Tech Xplore. “We were inspired by the rapid development of AI applications as well as Google’s TPU. From ChatGPT to Sora, artificial intelligence is ushering in a new revolution, but traditional silicon-based semiconductor technology is increasingly unable to meet the needs of processing massive amounts of data. We have come up with a solution to this global challenge.”

In computing, systolic arrays are networks of processors that rhythmically calculate data and let it flow freely, much like blood flows through the human body. Zhang and his colleagues developed a new, efficient systolic array architecture using carbon nanotube transistors, field-effect transistors (FETs) with channels made of carbon nanotubes instead of conventional semiconductors. Building on this new architecture they developed, they created the world’s first reported carbon nanotube TPU.

“The chip is composed of 3,000 carbon nanotube field-effect transistors, organized into 3*3 processing units (PEs),” Zhang explained. “These 9 PEs form a systolic array architecture, which can perform two-bit integer convolution and matrix multiplication operations in parallel.”

The tightly coupled architecture introduced by Zhang and colleagues supports systolic input data flow. This data flow through the architecture reduces read and write operations of static random access memory (SRAM) components, resulting in significant energy savings.

“Each PE receives data from its upstream neighbors (top and left), independently calculates a partial result on its own, and passes it downstream (right and bottom),” Zhang said. “Each PE is designed for 2-bit MAC and matrix multiplication on signed and unsigned integers. Combined with the systolic data stream, the CNT TPU could accelerate convolution operations in NN applications.”

The system architecture proposed by the team was carefully designed to accelerate tensor operations performed by artificial neural networks, easily moving from integer convolutions to matrix multiplications. The tensor processing chip they developed based on this architecture could be a crucial step for the development of new high-performance integrated circuits based on low-dimensional electronics.

“Based on our carbon-based tensor processor chip, we have built a five-layer convolutional neural network that can perform image recognition tasks with an accuracy rate of up to 88% and a power consumption of only 295 μW, which is the lowest power consumption among all new convolutional acceleration hardware technologies,” Zhang said.

“The system simulation results show that the carbon-based transistor using the 180nm technology node can achieve 850MHz and the energy efficiency exceeds 1TOPS/w, which shows obvious advantages over other device technologies at the same technology node.”

Overall, the results of the researchers’ initial simulations and tests highlight the potential of their carbon-based TPU, suggesting that it could be well-suited to running computer models based on machine learning. In the future, their chip could display greater computing power and be more energy efficient than existing semiconductor-based devices.

The research team’s efforts could eventually help speed up the operations of convolutional neural networks while reducing their energy consumption. In the meantime, Zhang and his colleagues plan to further increase the performance, energy efficiency and scalability of their chip.

“The performance and energy efficiency of this approach could be further improved, for example, by using aligned semiconducting CNTs as channel materials, reducing the transistor size, increasing the number of PE bits, or implementing CMOS logic,” Zhang added.

“The CNT TPU could also be built in BEOL in a silicon fab for three-dimensional integration: i.e., a silicon processor on the bottom with a CNT TPU on top as a co-processor. Additionally, 3D monolithic integration of multilayer CNT FETs could be investigated for the potential benefits of reduced latency and higher bandwidth.”

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