Engineers Develop New Low-Power Two-Dimensional Field-Effect Transistor

A team of electrical and computer engineers from the Shanghai Institute of Microsystems and Information Technology, Chinese Academy of Sciences, together with a colleague from the City University of Hong Kong and another from Fudan University, have developed a new, low-power two-dimensional field-effect transistor (FET) that could allow smartphones to need to be recharged less often.

In their article published in the journal NatureThe group describes how they overcame the problems of high gate leakage and low dielectric strength that have thwarted other researchers seeking to create smaller, thinner computer chips. Two of the team members (Ziao Tian and Zengfeng Di) published a Research Briefing, summarizing their work in the same issue of the journal.

For several years, computer engineers have been looking for new materials that will allow silicon field-effect transistors to be further miniaturized. This will allow more features to be added to phones and other devices without making them larger. It is also a necessity for the development of 5G devices that will be equipped with AI applications that are still in development.

The size of devices used in IoT applications will also need to be reduced. Current materials are already beginning to suffer from short-channel effects. Many in the industry see 2D materials as the future of these devices, as they would allow thickness to be reduced to just a few atoms.

Unfortunately, most of these efforts have run into problems with fluid interactions between 2D materials and the other parts that need to connect to them. More recently, some researchers have begun to look at thin metal oxides as a possible solution. In this new effort, the research team used single-crystal aluminum oxide that is only 1.25 nm thick.

The researchers noted that each of the FETs they created had an aluminum gate that was only 100 µm wide and 250 nm long. To ensure complete isolation, they left a gap between the gates. To create their FETs, they used standard van der Waals transfer methods to properly align the materials on the underlying wafer before moving the stack in a single step. The team describes the resulting product as a 2D FET with high-quality dielectric interfaces.

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