Morphology and electrical characteristics of MoS2 transistors with Pt/h-BN gate stack. (a) SEM image of a transistor with Pt/h-BN/MoS2 structure, in which the h-BN is CVD grown and the MoS2 is mechanically exfoliated. The length and width of the gate are 0.5 µm × 9 µm, scale bar: 2 µm. The thickness of the h-BN in this sample is about 8 nm. The source and drain electrodes are fabricated from gold by magnetron sputtering. The output characteristics and transfer characteristics of the FET device are shown in (b) and (c). (d) Optical microscope image of an all-CVD transistor with Pt/h-BN/MoS2 gate stack, scale bar: 25 µm. (e) Transfer characteristics for 20 devices like those in panel (d) in the dark and under illumination, confirming their correct use as photodetectors. The low currents (caused by non-optimized Schottky contacts between the MoS2 channel and the Au source/drain electrodes) are even beneficial in this application to reduce power consumption. (e) The gate current density versus gate voltage for the same 20 devices is measured in panel (e), showing no detectable gate leakage current. Credit: Shen et al.
Two-dimensional (2D) semiconductor materials exhibit distinct optoelectronic properties that could be advantageous for the development of ultrathin and tunable electronic components. Despite their potential advantages over bulk semiconductors, optimal interfacing of these materials with gate dielectrics has so far proven challenging, often resulting in interfacial traps that rapidly degrade transistor performance.
Researchers from King Abdullah University of Science and Technology (KAUST), Soochow University, and other institutes around the world recently presented an approach that could enable the fabrication of higher-performance transistors based on 2D semiconductors. Their proposed design, described in a paper published in Natural electronicsinvolves the use of hexagonal boron nitride (h-BN) dielectrics and high cohesive energy metal grid electrodes.
“Initially, we found that when we use platinum (Pt) as the anode, the h-BN stack is less likely to trigger dielectric breakdown,” Yaqing Shen, first author of the paper, told Tech Xplore. “Based on this finding, we designed our experiments and found that Pt/h-BN gate stacks have 500 times lower leakage current than Au/h-BN gate stacks and have a high dielectric strength of at least 25 MV/cm. This gave us the idea of using CVD h-BN as the gate dielectric in 2D transistors.”
Shen, Professor Mario Lanza and their colleagues fabricated more than 1,000 devices using chemically vapor-deposited h-BN as the dielectric. When they evaluated these devices, they found that h-BN gate dielectrics were most compatible with high-cohesive-energy metals, such as platinum and tungsten (W).
“To manufacture transistors with a vertical Pt/h-BN/MoS2 structure, we started by cleaning a SiO2/Si substrate using ultrasonic baths in acetone, alcohol, and deionized water,” Shen explained. “The source and drain electrodes (Ti/Au) were patterned on this substrate using electron beam lithography and deposited by electron beam deposition. Subsequently, MoS2 was exfoliated from a natural crystal and transferred onto these electrodes to form the channel. The CVD h-BN film was transferred onto this structure by wet transfer.
In the final step of their transistor manufacturing process, the researchers patterned the Pt gate electrode using electron beam lithography and then deposited it using a technique known as electron beam evaporation. The clean van der Waals interface between MoS2 and the h-BN in the team’s transistor improves its reliability and performance, minimizing defects and improving gate control.
“We found that contrary to the belief that CVD h-BN is a poor gate dielectric, selection of the right metal electrodes allows its efficient use in MoS field-effect transistors2 “The channels,” Shen said. “MoS2 and h-BN form a clean van der Waals interface, which improves reliability. Our results show that the use of high cohesive energy metals such as Pt and W makes CVD h-BN an efficient gate dielectric in 2D transistors.”
This research team’s approach to fabricating 2D semiconductor-based transistors has so far shown great promise, reducing current leakage and enabling high dielectric strengths of at least 25 MV cm-1Initial tests revealed that the Pt- and W-based gate electrodes reduced leakage current through the h-BN dielectrics by a factor of about 500 compared to similar transistors with gold (Au) electrodes.
Shen and his colleagues’ recent work could facilitate the use of 2D materials for the fabrication of reliable semiconductor microelectronic circuits and devices. Other research groups may soon explore similar approaches and materials, which could lead to the development of other high-performance 2D semiconductor-based devices.
“As the next step in our research, we plan to develop ultra-small (nanoscale) fully 2D transistors to help extend Moore’s Law,” Shen added. “We also want to solve the contact issues between 2D channels and electrodes to improve device performance.”
More information:
Yaqing Shen et al., Two-dimensional material-based transistors using hexagonal boron nitride dielectrics and high cohesive energy metal gate electrodes. Natural electronics(2024). DOI: 10.1038/s41928-024-01233-w
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